1. Field
The embodiments discussed herein relate to a receiving circuit and a sampling clock control method.
2. Description of the Related Art
A number of input/output (I/O) channels on a system, a substrate or a semiconductor chip may increase. In order to transmit and receive signals through multiple channels, a clock data recovery (CDR) circuit supports multiple channels. In order to support multiple channels, oversampling may be performed.
Related art are disclosed in Japanese Laid-open Patent Publication No. H11-168455, Japanese Laid-open Patent Publication No. H10-32566, Japanese Laid-open Patent Publication No. 2009-77134 and the like.